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[Other resource] fir-vhdl

Description: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Platform: | Size: 5335 | Author: MAX | Hits:

[Other] 用窗函数法设计FIR滤波器

Description: 用矩形窗、三角窗，汉宁窗，海宁窗等多种窗口设计有限长单位脉冲响应滤波器-with rectangular windows, triangular windows, Hanning window, multiple windows Haining window design finite impulse response filter units
Platform: | Size: 6144 | Author: 孙涛 | Hits:

[VHDL-FPGA-Verilog] FIRvhdl

Description: 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Platform: | Size: 3072 | Author: 达闻西 | Hits:

[VHDL-FPGA-Verilog] fir_filter

Description: 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
Platform: | Size: 3072 | Author: li | Hits:

[VHDL-FPGA-Verilog] FIR31

Description: 设计一个线性相位FIR滤波器（31阶） 输入8位，输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。 输入信号范围 [±99，0，0，0， ±70，0，0，0， ±99，0，0，0， ±70，…]-Design a linear phase FIR filter (31 bands) 8 input, 8 output, H (n) = (1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69111128111, ... ... 2,1) H (n) has a symmetry. Input signal range [± 99,0,0,0, ± 70,0,0,0, ± 99,0,0,0, ± 70, ...]
Platform: | Size: 2641920 | Author: 陈金立 | Hits:

[VHDL-FPGA-Verilog] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152576 | Author: 冯申 | Hits:

[Communication-Mobile] 2005612300003FIRVHDL

Description: 自己在一个通信项目中设计的滤波器，在传统设计的基础上作了改进，具有更好的特性。-himself in a communications projects designed filter, in the traditional design made on the basis of improvement has better features.
Platform: | Size: 26624 | Author: 小令 | Hits:

[VHDL-FPGA-Verilog] FIR_vhdl

Description: 基本FIR滤波器的VHDL源代码及其测试程序。-basic FIR filter VHDL source code and testing procedures.
Platform: | Size: 1024 | Author: qjyong | Hits:

[Other] 66_FIR11

Description: VHDLfir滤波器资料 可以实际上 一落千丈-VHDLfir filter information can be actually nosedived
Platform: | Size: 7168 | Author: jinlong | Hits:

[Communication-Mobile] VHDL_FIR11

Description: 用VHDL实现查找表方式的FIR滤波器-using VHDL search forms for the FIR filter
Platform: | Size: 11264 | Author: 梁立林 | Hits:

[Communication-Mobile] FirGen_V1.1

Description: 產生你所需要的FIR濾波器，可以產生VHDL格式之源碼。-Have you need FIR filter, can generate VHDL source code format.
Platform: | Size: 368640 | Author: hcjian | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[MacOS develop] firVerilog

Description: 里面是一个FIR滤波器的VHDL语言 具体的功能里面有详细的介绍 对毕业设计者很有帮助的 -There is a FIR filter VHDL language specific features which are detailed introduction to the graduate designers helpful
Platform: | Size: 4096 | Author: 丛宇 | Hits:

[Communication-Mobile] suAra6Rm

Description: fir滤波器的Verilog程序,看看吧，还不错！-fir filter Verilog procedures, take a look at it, but also good!
Platform: | Size: 4096 | Author: wanghua | Hits:

[VHDL-FPGA-Verilog] DIGTAL_FIR

Description: 环路滤波器的设计，基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Platform: | Size: 774144 | Author: 梁大法 | Hits:

[VHDL-FPGA-Verilog] firOK

Description: fir滤波器的设计，此滤波器 Fs为44kHz,Fc为10.4kHz。-fir filter design, this filter Fs for 44kHz, Fc for 10.4kHz.
Platform: | Size: 987136 | Author: fdf | Hits:

[VHDL-FPGA-Verilog] DA_FIR

Description: 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Platform: | Size: 531456 | Author: CH | Hits:

[VHDL-FPGA-Verilog] tdmddc_v61

Description: Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
Platform: | Size: 54272 | Author: | Hits:

[VHDL-FPGA-Verilog] FIR-VHDL

Description: 15阶FIR滤波器的设计VHDL代码 ，包括顶层模块及各模块的VHDL设计代码-15 order FIR filter design VHDL code, including the top-level module and each module VHDL design code
Platform: | Size: 2048 | Author: 张宇航 | Hits:

[Other] VHDL-FIR-filters

Description: ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has been synthesized with Xilinx Vivado 2015.1 to confirm the correct DSP cascade chain is inferred.
Platform: | Size: 37888 | Author: Abkoti | Hits:
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